Silicon on Sapphire
Silicon on Sapphire wafers are comprised of R-Plane (1102) sapphire wafers with a deposited layer of silicon on their polished surface.
When cut at the R-plane the oxygen atoms of the sapphire wafer mirror the symmetry of the silicon crystal at (100) orientation enough that silicon crystal can be grown on the surface.
Silicon on Sapphire wafers are used in radio frequency integrated circuits (RFIC). Chips made using Silicon-on-Sapphire are used in mobile devices and other electronics where the low power consumption, resistance to radiation and durability and stability over a wide temperature range allow them to out-perform other Silicon-on-Insulator devices.
Standard Specification
| Item | Specification | ||||
|---|---|---|---|---|---|
| Substrate | Diameter | 3″ | 4″ | 6″ | 8″ |
| Material | 99.996% Purity Single Crystal Al2O3 (Sapphire) | ||||
| Grade | Prime, Epi-ready | ||||
| Orientation | R-Plane (1-102), (10-12), (0112) | ||||
| Off-Cut | +/-1.0 degree | +/- 0.5 degree | +/-1.0 degree | +/-20 degree | |
| Diameter (mm) | 76.0 (+/-0.5mm) | 100 (+/-0.2mm) | 150mm (+/-0.3mm) | 200mm (+/-0.5mm) | |
| Thickness (um) | 350/500 (+/-20um) | 460/530 (+/-20um) | 600 (+/-20um) | 725 (+/-20um) | |
| Primary Flat | 45degree Counter-Clockwise from Axis C projection on R-plane | ||||
| Flat Length (mm) | 22.0 (+/-3.0mm) | 32.5 (+/-2.5mm) | 47.5/57.5 (+/-2.5mm) | Notch per SEMI M1-1105 | |
| Front Surface | Epi-Ready Polished Surface Ra ≤0.3nm | ||||
| Back Surface | Finish as lapped (Ra =0.6um) or Optical Polish | ||||
| Laser Marking | SEMI Standard LM on back of wafer | ||||
| TTV | ≤25um | ≤15um | ≤12um | ≤20um | |
| BOW | ≤25um | ≤20um | ≤30um | ≤20um | |
| WARP | ≤25um | ≤20um | ≤30um | ≤40um | |
| Flatness | ≤20um | ≤12um | ≤8um | ≤15um | |
| Packaging | SEMI Standard, Argon Atmosphere vacuum sealed in class 100 clean room | ||||
| Edge Exclusion (mm) | 2 | 3 | 4 | 5 | |
| Notes | Metallic Contamination: <5e10 atoms/cm² by VPD for Ca, Na, K, Cr, Zn, Fe, Cu and Ni;LPD:≤40 @ ≥0.2microns | ||||
| EPI Layer | Thickness | Silicon Epi Layer centre point: 0.1~6.0um | |||
| <10% | |||||
| Si (100) Epi on R-Plane Sapphire Polished Side | |||||
| Si layer epitaxially deposited directly onto sapphire substrate in accordance with SEMI M4-1296 | |||||
| Intrinsic (Non intentionally doped) type; N-tye(Phos. Doped); P-type (Boron Doped) | |||||
| 0.1~100Ωcm or ≤100Ωcm | |||||
| (for particles greater than 2 microns): < 2 per cm² | |||||
For R-Plane sapphire wafers please see our sapphire wafer section.
